Generally, shallow trench isolations (STIs) are used to separate and isolate active areas on a semiconductor wafer from each other. These STIs have historically been formed by etching trenches, sometimes referred to as gaps, overfilling the trenches with a dielectric such as an oxide, and then removing any excess dielectric with a process such as chemical mechanical polishing (CMP) or etching in order to remove the dielectric outside the trenches. This dielectric helps to electrically isolate the active areas from each other.
However, as circuit densities continue to increase, the widths of these gaps decrease, thereby increasing gap aspect ratios, which are typically defined as the gap height divided by the gap width. As a result, it is very difficult to fill these narrow and deep gaps completely with a gap-fill dielectric material. Incomplete filling results in unwanted voids and discontinuities in the gap-fill dielectric material as well as inclusion of unwanted material. These voids and inclusions result in inadequate isolation between active areas. Electrical performance of a device with inadequate isolation is poor and device yield is reduced.